1. Field of the Invention
The present invention relates to the field of sequential digital logic design. Specifically, the present invention relates to a method and apparatus for asynchronously transferring data from a first synchronous sequential logic circuit which derives its clock source from a first clock to a second synchronous sequential logic circuit which derives its clock source from a second clock, whereby metastability of the second synchronous sequential logic circuit is avoided.
2. Description of Related Art
Components of digital logic circuits are characterized as either combinational or sequential. Combinational logic circuits are comprised of logic gates that, generally, perform the logical operations of Boolean AND, OR and NOT. The output of such a gate is dependent only upon its inputs. By contrast, sequential logic circuits are comprised of memory elements, such as flip-flops or registers, that maintain state information, that is, that store a value, and combinational logic. The output of such a memory element is a function of not only its inputs, but of the contents, or present state, of the memory element as well.
Sequential logic circuits are further characterized as either asynchronous (unclocked) or synchronous (clocked). Whereas inputs to an asynchronous sequential logic circuit can change at any time, and thus, the state of the circuit is capable of changing at any time, the inputs to a synchronous logic circuit are capable of changing the state, and thus, the output of the circuit, only at specific times, as defined by a particular clocking or timing methodology.
As is well known to those of ordinary skill in the art of digital logic circuit design, clocked or synchronous sequential circuits are triggered, that is, they change state, according to clock pulses input to the circuit. As the output of a memory element is a signal representing the current state of the memory element, it follows that the output of a clocked sequential circuit is updated in synchronization with clock pulses provided as input to the circuit.
A common timing methodology in the art is edge-triggered clocking, wherein a memory element is triggered, i.e., the one or more inputs to the memory element are sampled, during either the leading (rising) or trailing (falling) edge of a clock signal supplied as input to the memory element. Thus, for example, a trailing edge triggered flip-flop changes state on the trailing edge of a clock signal in transition and maintains that state for one complete clock cycle, that is, until another trailing edge of a clock signal is detected. In the event a flip-flop is required to change state with less frequency than every clock cycle, for example, when propagational delay of a signal through combinational logic coupled between a first and second flip-flop exceeds the time to complete one clock cycle, a control signal provided as input to the second flip-flop may further control at which trailing edge of a clock signal it may change state, so that it is capable of changing state only after the signal output from the first flip-flop has arrived at one of its inputs.
When a memory element such as a flip-flop or register is triggered by the edge of a clock signal, inputs to the memory element should be stable at that time. If one or more inputs to a memory element are changing state at the time at which a clock edge is received (and the inputs sampled), the state and, thus, the output of the memory element may be unstable. When one or more inputs of a memory element are in transition at the time the memory element is triggered, thereby causing the state and output to be indeterminate, the memory element is said to be in a metastable state.
To avoid metastability, there are fundamental timing requirements which digital logic circuit designers should give consideration. One such timing requirement is setup time, hereinafter referred to as T.sub.setup, which defines that period of time immediately prior to receiving a clock edge in which inputs to the memory element must be stable and valid, either high or low. Likewise, another fundamental timing requirement, hold time, hereinafter referred to as T.sub.hold, defines that period of time immediately following reception of a clock edge in which inputs to the memory element must be stable and valid. Metastability is the resulting behavior of a synchronous memory element if such fundamental timing requirements are not met. Thus, each input to a synchronous memory element must be stable, that is, maintain a voltage level representing a valid logic value so that a single valid output logic value is detected, for a window of time equal to T.sub.setup +T.sub.hold so as to avoid metastability. It should be further noted, as is well known to those of ordinary skill in the art, metastability can manifest itself in many ways, including, but not limited to, an unpredictable output logic value, oscillation of the output value, indeterminate voltage level of the output representing a illegitimate logic value somewhere between a valid high or valid low logic value, and an indeterminate period of instability.
When coupling two external devices together, such as a digital computer and an input/output device, it may not be possible or advantageous for all the logic circuitry involved to derive its clock source from the same clock. In such a case, a plurality of clocks, each providing a clock signal to an exclusive region of the logic circuitry of a device, or each providing a clock signal to the logic circuitry of separate, external, devices may be employed. Thus, in such circumstances, multiple clock domains may exist. Components of a synchronous logic circuit which derive their clock source from the same clock are in the same clock domain. In contrast, components of synchronous logic circuits, or synchronous logic circuits, which derive their clock source from different, independent clocks are in different clock domains.
Signals transferred between a first synchronous logic circuit in a first clock domain and a second synchronous logic circuit in a second clock domains are transferred asynchronously. The problem inherent in such a transfer is that a signal transferred from the first synchronous logic circuit may be in transition at the same time a clock signal for the second synchronous logic circuit triggers the memory element receiving as input the signal from the first synchronous logic circuit, thereby inducing metastability. In the prior art, to prevent an asynchronous signal arriving at the second logic circuit from being in transition during triggering of the second logic circuit, the first and second circuits use control signals in the form of a two-way handshake to synchronize the asynchronously transferred signal.
Referring to FIG. 1, an example of the logic needed to implement the prior art, two-way handshake method of asynchronous transfer between a first synchronous logic circuit and a second synchronous logic circuit is shown. Circuit 100 is comprised of two separate, synchronous sequential logic circuits, each having their own clock, namely, the logic circuit in source clock domain 101 and the logic circuit in destination clock domain 102. The circuit in source clock domain 101 is comprised of source register 103 and source control logic 105, which in turn, comprises a finite state machine and two flip-flops, 107a and 107b, hereinafter collectively referred to as synchronizer chain 107. The circuit in destination clock domain 102 is comprised of destination register 104, and destination control logic 106, which in turn, comprises a finite state machine and two flip-flops, 108a and 108b, hereinafter collectively referred to as synchronizer chain 108. In this example, data is transferred from source register 103 to destination register 104. Source control logic 105 and destination control logic 106 control the sequence of operations and synchronize the handshake signals DATA.sub.-- GNT 113 and DATA.sub.-- ACK 114 by way of synchronizer chain 107 and synchronizer chain 108, respectively. In this way, source control logic 105 and destination control logic 106 cooperate to asynchronously transfer data from the logic circuit of source clock domain 101, specifically, source register 103, to the logic circuit of destination clock domain 102, specifically, destination register 104.
A synchronizer chain is commonly constructed of a plurality of flip-flops coupled in sequence, wherein each flip-flop may be referred to as a stage in the synchronization chain. For example, synchronizer chain 107 in the prior art shown in FIG. 1 is comprised of two flip-flops in sequence, the output of flip-flop 107a coupled to the input of flip-flop 107b. It should be noted that although in this example the synchronization chain has a depth of two, that is, two flip-flops coupled in sequence, a synchronization chain can be of any depth. The effectiveness of a given synchronization stage is directly related to how quickly a flip-flop at that stage can resolve metastability, which, generally, is a function of the propagational delay of the flip-flop, and how long the flip-flop has to resolve the metastability before the following stage samples its output, that is, the frequency of operation. Generally, as the number of flip-flops chained together increases, the probability that the output of the final flip-flop is metastable decreases significantly. However, since metastability may have occurred earlier in the synchronization chain, the logical value output at the end of the synchronization chain may not reflect the original state of the signal input to the synchronization chain. Thus, while the occurrence of metastability may be minimized through the use of a synchronization chain, the accuracy of the logical value of the signal, in this example, a control signal, output from the chain is still suspect.
Because destination register 104 by itself does not know when source register 103 has data available for transfer over line 112, it is necessary that a control signal furnish this information. When asserted, the data grant (DATA.sub.-- GNT 113) signal sent by source control logic 105 informs destination control logic 106 when source register 103 has data available and is ready to transmit. Moreover, since source control logic 105 should be informed when data has been accepted by destination register 104, it is necessary that a control signal furnish this information. The data acknowledge (DATA.sub.-- ACK 114) signal sent by destination control logic 106, when asserted, informs source control 105 that destination register 104 has received the data from source register 103 by way of line 112. Source control logic 105 assures that the contents of source register 103 do not change after DATA.sub.-- GNT 113 is asserted until it detects the assertion of DATA.sub.-- ACK 114.
A significant amount of delay is incurred to complete a two-way handshake using control signals DATA.sub.-- GNT 113 and DATA.sub.-- ACK 114 due to the time required for flip-flops 108a and 108b to synchronize DATA.sub.-- GNT 113 and flip-flops 107a and 107b to synchronize DATA.sub.-- ACK 114. Referring now to FIG. 2, waveform 201 represents the clock signal for the circuitry in source clock domain 101, whereas waveform 205 represents the clock signal for the circuitry in destination clock domain 102. Waveform 202 represents the asynchronous data grant signal DATA.sub.-- GNT 113 sent by source control logic 105 when source register 103 has new data available to transmit over line 112. The presence of valid data in waveform 204 beginning at time 212 coincides with the assertion of the data grant signal DATA.sub.-- GNT 113. The data grant signal DATA.sub.-- GNT 113 can arrive at destination control logic 106 in destination clock domain 102 at any time, thus, synchronizer 108 synchronizes the signal, producing as output a synchronized data grant signal represented by waveform 206. The delay incurred to synchronize the data grant signal DATA.sub.-- GNT 113 is shown at 208. Upon receiving the synchronized data grant signal 206 via line 116 (FIG. 1), destination register 104 begins receiving valid data present on line 112.
Waveform 207 represents the asynchronous data acknowledge signal DATA.sub.-- ACK 114 sent by destination control logic 106 when destination register 104 has received valid data from source control register 104 by way of line 112. The data acknowledge signal DATA.sub.-- ACK 114 can arrive at source control logic 105 in source clock domain 101 at any time, thus, synchronizer 107 synchronizes the signal, producing as output a synchronized data acknowledge signal represented by waveform 203. The delay incurred to synchronize the data acknowledge signal DATA.sub.-- ACK 114 is shown at 209. Upon receiving the synchronized data acknowledge signal 203 via line 115 (FIG. 1), the contents of source register 103 can thereafter change value as shown at time 213. However, until the handshake is complete at time 214, new data in source register 103 is not available for transmission over line 112. Thus, the method of asynchronously transferring data using two-way handshake control signals limits the rate at which data can be transferred between synchronous logic circuits having different clock domains. While logic capable of buffering data could be employed, the logic is difficult to implement and error prone. And while buffering will allow the peak data transfer rate to increase, the overall data transfer rate is ultimately limited by the rate at which data can be asynchronously transferred across logic circuits in different clock domains. Moreover, the synchronization of the handshake signals further limits the rate at which data can be transferred. Finally, a method of asynchronously transferring data not requiring the two-way handshake control signals would reduce the complexity of the control logic managing the flow of data between logic circuits having different clock domains.
Thus, a better method and apparatus for asynchronously transferring data from a first synchronous sequential logic circuit which derives its clock source from a first clock to a second synchronous sequential logic circuit which derives its clock source from a second clock, whereby metastability of the second synchronous sequential logic circuit is avoided, is needed.